1. Field of the Invention
This invention relates generally to floating gate memory devices such as an array of flash electrically erasable and programmable read-only memory devices (EEPROMs). More particularly, the present invention relates to an improved method for bulk (or byte) programming a flash EEPROM device having a floating gate structure.
2. Description of the Prior Art
As is generally known in the art, there exists a class of non-volatile memory devices referred to as "flash EEPROMs" which has recently emerged as an important memory device by combining the advantages of EPROM density with EEPROM electrical erasability. Such flash EEPROMs provide electrical erasing and a small cell size. The operation and structure of such flash EEPROMs is discussed in U.S. Pat. No. 5,077,691 to Sameer S. Haddad et al. issued on Dec. 31, 1991, which is assigned to the same assignee as in the present invention and is hereby incorporated by reference in its entirety. The '691 patent discloses a flash EEPROM cell array which is erased by applying a zero reference voltage to the bulk substrate of the cell, a relatively high negative voltage to the control gate of the cell, and a relatively low positive voltage to the source region of the cell. During the sector-programming mode of operation, a relatively high positive voltage (i.e., +12 V) is applied to the control gates via wordlines of the selected sectors while zero volts are applied to the control gates of the memory cells in the non-selected sectors. Further, the source regions of all transistors in the selected sectors are connected to a ground potential of zero volts, and the drain regions thereof are raised to an intermediate high positive level of approximately +6.5 volts.
Another discussion regarding the operation and structure of flash EEPROM devices is described in U.S. Pat. No. 5,126,808 to Antonio J. Montalvo et al. issued on Jun. 30, 1992, which is assigned to the same assignee as in the present invention and is also hereby incorporated by reference in its entirety. In the '808 patent, there is disclosed a flash EEPROM array with page erase architecture in which a selected page of the memory array can be erased and replaced with new data without affecting the other pages of the memory array. Erasure of a flash EEPROM cell in the array is accomplished by use of a negative voltage on the control gate of the EEPROM cell.
Each of the plurality of flash EEPROM cells may be formed on a semiconductor substrate, typically of a p-type conductivity. Drain and source regions are formed in the upper portions of the p-type substrate by using a diffusion method such as ion-implantation technique with an n-type dopant of arsenic or phosphorus. The formation of the n-type drain and source regions define a channel region on the p-type substrate. A tunneling oxide film is formed on the channel region in the p-type substrate. A conductive polysilicon floating gate is formed on the tunneling oxide film. An interpoly dielectric is formed on the floating gate. A polysilicon control gate is insulatively formed on the interpoly dielectric.
According to conventional operation, the flash EEPROM cell is erased by applying a positive voltage to the source region while the control gate is grounded or biased to a negative voltage. In flash EEPROM arrays, all of the cells therein are usually erased in bulk (i.e., either the entire chip or by sectors each having a large number of floating gate transistors). This is due to the fact that their source regions are all tied to a common source line. On the other hand, the flash EEPROM cell is programmed by applying a relatively high voltage to the control gate and a moderately high voltage to the drain region. The source region is connected to a ground potential.
A number of disadvantages may be encountered with the conventional way in which the flash EEPROM cells are programmed. One drawback is because of the different voltages required to be applied to the control gates and source regions (i.e., +12 V and +6 V) during programming. Thus, it is frequently necessary to provide at least two power supplies for generating these voltages. Further, the magnitude of the programming current tends to be relatively high, on the order of approximately 400 .mu.A per cell. As a consequence, the power requirement of a memory chip having one million or more memory cells (a one megabit chip) can be excessive. There has been a long felt need in the industry to develop a flash EEPROM chip which can be operated by only a single, low voltage power supply (i.e., +3 V) that has a low current requirement (i.e., 1 .mu.A per cell).
The second drawback of the conventional programming technique arises from the fact that a relatively high field is generated between the drain and the substrate during programming (p-type substrate has 0 V applied and the n-type drain region is at +6 V). As a result, there may be caused high energy holes ("hot" holes generated by a so-called "impact ionization") to be formed at the surface portion of the channel near to the drain-to-substrate junction, thereby producing damage thereto so as to cause severe degradation in its performance and reliability.
A third drawback associated with the conventional programming technique is that the bulk programming time is relatively long. For the conventional method (using hot-carrier injection), the byte programming is less than 10 .mu.S. However, there is needed to be programmed thousands of bytes (i.e., 64K bytes for a sector size of 512K bits). Further, this is done serially. Thus, the total programming time for the whole sector will be in the order of a second. It would therefore be desirable to provide an EEPROM chip which has a relatively fast bulk programming time for the whole sector, on the order of less than 100 .mu.S.
As is generally known, the substrate is typically common for the core devices and the peripheral circuitry. In order to have the capability of applying a substrate voltage to the cells in the core array but yet maintain the substrate at an independent potential, typically at 0 volts, the core array will be located inside a large p-well area. For example, such use of a p-well area is demonstrated in a memory array architecture which is known in the prior art and is sometimes referred to as DINOR (divided bit line NOR) flash memory. For a more detailed discussion of this DINOR type architecture, reference is made to an IEEE paper entitled "Memory Array Architecture and Decoding Scheme for 3 V Only Sector Erasable DINOR Flash Memory" by Shin-ichi Kobayashi et al., IEEE Journal of Solid-State Circuits, Vol. 29, No. 4, April, 1994, pp. 454-460. This article is incorporated herein by reference.
As defined herein, the term "charging" refers to placing negative charges on the floating gate and is typically referred to a "programming." The term "discharging" refers to extracting negative charges from the floating gate and is typically referred to as "erasing." However, for the DINOR type architecture the term "charging" is used to mean "erasing" since it is a bulk operation and the term "discharging" is used to mean "programming." In the above-mentioned article, there is described a bulk charging method for the memory array using Fowler-Norheim tunneling which requires a high field to be applied to the cell. In other words, the voltage condition of the DINOR cell in the erase operation for the selected sector is +10 V on the word lines (control gates) and -8 V on the p-well and the sources. However, this technique suffers from the disadvantages of high voltages and slow bulk charging.